Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. Support circuitry is required to perform write, read, and erase operations of the memory cells in the vertical NAND strings. The support circuitry can be provided by forming complementary metal oxide semiconductor (CMOS) devices on a same substrate as the three-dimensional memory device. Alternatively, the support circuitry can be provided in a support die that is bonded to a memory die including a three-dimensional memory device.